Tygomuro Current sense positive terminal when charging relative to SR2. D Low Supply Current of? This bit indicates a short-circuit in the charge direction. Supply voltage ba PACK.
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The bq also integrates an I2C compatible interface to extract battery parameters such as cell voltages and control output status. Other parameters such as current protection thresholds and delays can be programmed into the bq to increase the flexibility of the battery management system.
The bq provides safety protection for overcharge, overload, short-circuit, overvoltage, and undervoltage conditions in conjunction with the battery management host. In overload and short-circuit conditions, the bq turns the FET drive off autonomously dependant on the internal configuration setting. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
It enables cell balancing, enters different power modes, sets overload levels, sets the overload blanking delay time, sets short-circuit threshold levels for charge and discharge, and sets the short-circuit blanking delay time. Cell balancing of each cell is performed via a cell bypass path, which is enabled via the internal control register accessible via the I2C compatible interface.
The maximum bypass current is set via an external series resistor and internal FET on resistance typical ? These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Once V PACK is above the start-up voltage, it can fall down to the minimum supply voltage and still meet the specifications of the bq A Ship current 0. Sense voltage input terminal for second most positive cell, balance current input for second most positive cell and return balance current for most positive cell. Sense voltage input terminal for third most positive cell, balance current input for third most positive cell and return balance current for second most positive cell.
Sense voltage input terminal for least positive cell, balance current input for least positive cell and return balance current for third most positive cell. Sense voltage input terminal for most negative cell, return balance current for least positive cell. Current sense positive terminal when charging relative to SR2 Current sense negative terminal when discharging relative to SR2 current sense terminal Digital input that provides the timing clock for the OC and SC delays and also acts as the watchdog clock.
Output of scaled value of the measured cell voltage. Analog ground pin and negative pack terminal Open-drain bidirectional serial interface clock with internal 10 k? Open-drain bidirectional serial interface data with internal 10 k? Connect to GND Open-drain output used to indicate status register changes. With internal k? The output is typically 3.
F and is also internally current limited. During normal operation, the regulator limits output current to typically 50 mA. Initialization The bq internal control circuit is powered by the REG voltage, which it also monitors. When the voltage at REG falls below 2. After start up, when the REG voltage is above 2. Overload Detection The overload detection is used to detect abnormal currents in the discharge direction. This feature is used to protect the pass FETs, cells and any other inline components from excessive current conditions.
The detection circuit also incorporates a blanking delay before driving the control for the pass FETs to the OFF state. The overload threshold can be programmed from 50 mV to mV in 5-mV steps with the default being 50 mV and hysteresis of 10 mV.
Short-Circuit Detection The short current circuit detection is used to detect abnormal current in either the charge or discharge direction. This safety feature is used to protect the pass FETs, cells, and any other inline components from excessive current conditions. The short-circuit threshold can be programmed from mV to mV in mV steps with the default being mV and hysteresis of 50 mV.
The delay time can be increased via the OLT register, which can be programmed for a range of 1 ms to 31 ms with steps of 2 ms. This register can be programmed from 0? The series element voltage is translated to a GND-based voltage equal to 0. This provides a range from 0 V to 4. The translation output is inversely proportional to the input using the following equation. Calibration of Cell Voltage Monitor Amplifier Gain The cell voltage monitor amplifier has an offset and to increase accuracy this can be calibrated.
There are a couple of method by calibration circumstance. The following procedure shows how to measure and calculate the offset and gain as one of example.
The purpose of this bypass path is to reduce the current into any one cell during charging to bring the series elements to the same voltage. Series resistors placed between the input pins and the positive series element nodes control the bypass current value. The typical thermistor resistance is 10 k? The default-state is OFF to conserve power. The maximum output impedance is ?. Once the watchdog has been started during this wake up period, it monitors the host for an oscillation stop condition, which is defined as a period of ?
The host can force any FET on or off only if the bq integrated protection control allows. These controls are only valid when not in the initialized state. Precharge and 0 V Charging—Theory of Operation The bq supports both a charger that has a precharge mode and one that does not. The bq also supports charging even when the battery falls to 0 V. Detail is described in the application section. Table 1. If change configuration, latest write data is valid.
The following table outlines the operational functions during these power modes. Table 2. The supply current of this mode varies as the host can enable and disable various power management features. On entry to this mode, all registers are masked off keeping their state.
The host controller can change the RAM registers via the I2C interface, but reading data is disabled until exit of Sleep mode. The bq acts as a slave device and does not generate clock pulses. The slave address for the bq is 7 bits and the value is 0x The bq is always regarded as a slave. The bq does not return a NACK for an invalid register address. The bq does not support the general code of the I2C specification, and therefore does not return an ACK. The bq does not support the address auto increment, which allows continuous reading and writing.
The bq allows data to written or read from the same location without resending the location address. These registers provide status, control, and configuration information for the battery protection system.
Table 3. For example, when the kHz input fails, the overload and short-circuit delay timers no longer function because they use the same WDI input. If the WDI input clock stops, these current protections do not function. WDF should be enabled at any time for maximum safety. OLV b4—b0 configuration bits with corresponding voltage threshold 0.
SCC b3—b0 : These bits select the value of the short-circuit voltage threshold with as the default. SCC b3—b0 with corresponding SC threshold voltage 0. SCC b7—b4 with corresponding SC delay time 0? SCD b3—b0 with corresponding SC threshold voltage with as the default. SCD b3—b0 : These bits select the value of the short-circuit voltage threshold 0. SCD b7-b4 with corresponding SC delay time 0?
In this case, the supply voltage for the device is too low to operate. There are 3 possible configurations for this function and the bq can be easily configured according to the application needs. The host charger is expected to provide a precharge function. The charger is expected to provide a precharge function.
The charger does not provide any precharge function. The charger is expected to provide the precharge function in this mode where the precharge current level is suitable to charge cells below a set level, typically below 3 V per cell. When the lowest cell voltage rises above this level, then a fast charging current is applied by the charger. For example: If the linear region is 0. But the VDS remains at 0. The signal timing is shown in Figure Although the current path is changed, the same precharging current is still applied.
When V BAT reaches the fast charging voltage typical 3 V per cell , the charger switches into fast charging mode. The application circuit is shown in Figure The charger is expected to provide the precharge function in this mode, where the charger provides a precharge current level suitable to charge cells below a set level, typically below 3.
When the lowest cell voltage rises above this level then a fast charging current is applied. When the charger is connected the voltage at PMS rises.